Computing memory systems generally include one or more dynamic random access memory (DRAM) integrated circuits, referred to herein as DRAM devices, which are connected to one or more processors. Multiple DRAM devices may be arranged on a memory module, such as a dual in-line memory module (DIMM). A DIMM includes a series of DRAM devices mounted on a printed circuit board (PCB) and are typically designed for use in personal computers, workstations, servers, or the like. There are different types of memory modules, including a load-reduced DIMM (LRDIMM) for Double Data Rate Type three (DDR3), which have been used for large-capacity servers and high-performance computing platforms. Memory capacity and/or bandwidth may be limited by the loading of the data query (DQ) bus and the command-address (CA) bus associated with many DRAM devices and DIMMs. LRDIMMs allow a somewhat increased memory capacity by using memory buffers (sometimes also referred to as registers) on each DIMM to buffer memory channel signals. Registered memory modules have a register between the DRAM devices and the system's memory controller. For example, a fully buffered DIMM architecture introduces an advanced memory buffer (AMB) between the memory controller and the DRAM devices on the DIMM. The memory controller communicates with the AMB as if the AMB were a memory device, and the AMB communicates with the DRAM devices as if the AMB were a memory controller. The AMB can buffer data, command and address signals. With this architecture, the memory controller does not communicate with the DRAM devices directly, rather the AMB is an intermediary for communication with the DRAM devices.
Lithographic feature size has steadily shrunk in each generation of dynamic random access memory components (DRAM). As a result, the device storage capacity of each generation has increased. Each generation has seen the signaling rate of interfaces increase, as well, as transistor performance has improved.
Unfortunately, one metric of memory system design which has not shown comparable improvement is the system capacity of a memory channel. Rather, this capacity has steadily eroded as the signaling rates have increased.
Part of the reason for this is the link topology used in some memory systems. When more modules are added to the system, the signaling integrity is degraded, and the signaling rate must be reduced, even for buffered solutions. Typical memory systems today are limited to just one or two modules when operating at the maximum signaling rate.